Negative-bias temperature instability

Negative-bias temperature instability (NBTI) is a key reliability issue in MOSFETs, a type of transistor aging. NBTI manifests as an increase in the threshold voltage and consequent decrease in drain current and transconductance of a MOSFET. The degradation is often approximated by a power-law dependence on time. It is of immediate concern in p-channel MOS devices (pMOS), since they almost always operate with negative gate-to-source voltage; however, the very same mechanism also affects nMOS transistors when biased in the accumulation region, i.e. with a negative bias applied to the gate.

More specifically, over time positive charges become trapped at the oxide-semiconductor boundary underneath the gate of a MOSFET. These positive charges partially cancel the negative gate voltage without contributing to conduction through the channel as electron holes in the semiconductor are supposed to. When the gate voltage is removed, the trapped charges dissipate over a time scale of milliseconds to hours. The problem has become more acute as transistors have shrunk, as there is less averaging of the effect over a large gate area. Thus, different transistors experience different amounts of NBTI, defeating standard circuit design techniques for tolerating manufacturing variability which depend on the close matching of adjacent transistors.

NBTI has become significant for portable electronics because it interacts badly with two common power-saving techniques: reduced operating voltages and clock gating. With lower operating voltages, the NBTI-induced threshold voltage change is a larger fraction of the logic voltage and disrupts operations. When a clock is gated off, transistors stop switching and NBTI effects accumulate much more rapidly. When the clock is re-enabled, the transistor thresholds have changed and the circuit may not operate. Some low-power designs switch to a low-frequency clock rather than stopping completely in order to mitigate NBTI effects.

Physics

The details of the mechanisms of NBTI have been debated, but two effects are believed to contribute: trapping of positively charged holes, and generation of interface states.

• preexisting traps located in the bulk of the dielectric are filled with holes coming from the channel of pMOS. Those traps can be emptied when the stress voltage is removed, so that the Vth degradation can be recovered over time.
• interface traps are generated, and these interface states become positively charged when the pMOS device is biased in the "on" state, i.e. with negative gate voltage. Some interface states may become deactivated when the stress is removed, so that the Vth degradation can be recovered over time.

The existence of two coexisting mechanisms has resulted in scientific controversy over the relative importance of each component, and over the mechanism of generation and recovery of interface states.

In sub-micrometer devices nitrogen is incorporated into the silicon gate oxide to reduce the gate leakage current density and prevent boron penetration. It is known that incorporating nitrogen enhances NBTI. For new technologies (45 nm and shorter nominal channel lengths), high-κ metal gate stacks are used as an alternative to improve the gate current density for a given equivalent oxide thickness (EOT). Even with the introduction of new materials like hafnium oxide in the gate stack, NBTI remains and is often exacerbated by additional charge trapping in the high-κ layer.

With the introduction of high κ metal gates, a new degradation mechanism has become more important, referred to as PBTI (for positive bias temperature instabilities), which affects nMOS transistor when positively biased. In this case, no interface states are generated and 100% of the Vth degradation may be recovered.

Modeling Approaches

NBTI modeling approaches can be broadly classified as empirical or physics-based.

The empirical power-law model is widely used due to its simplicity and simulation efficiency. It approximates the threshold voltage shift as:

${\displaystyle \Delta V_{\text{th}}(t)=A\cdot t^{n}}$

where ${\displaystyle A}$ is a prefactor influenced by electric field, oxide thickness, temperature, and process variation, and ${\displaystyle n}$ is the time exponent.^[1] While useful for estimating long-term aging trends, this model lacks physical insight into trap generation and does not account for recovery.

The R-D model is more computationally intensive but provides improved accuracy and predictive capabilities, especially in advanced nodes and for time-dependent recovery. The more physically accurate reaction–diffusion (R–D) model describes two interlinked processes as per ^[2][3]

Reaction Phase

Under negative bias and elevated temperature, a chemical reaction at the Si/SiO₂ interface breaks Si–H bonds, generating interface traps and releasing hydrogen:

${\displaystyle {\text{Si–H}}\rightleftharpoons {\text{Si}}^{+}+X_{\text{interface}}}$     (1)

The forward rate constant ${\displaystyle k_{f}}$ governs the rate of trap generation.

Diffusion Phase

The freed hydrogen diffuses away into the oxide bulk, reducing the local hydrogen concentration and triggering further Si–H dissociation. Upon stress removal, some hydrogen returns to re-passivate the traps:

${\displaystyle X_{\text{interface}}\rightleftharpoons X_{\text{bulk}}}$     (2)

This reversible diffusion explains the partial recovery observed in NBTI. The reverse process is controlled by a trap annealing rate constant ${\displaystyle k_{r}}$.

The time evolution of interface trap density ${\displaystyle N_{it}(t)}$ is modeled by the following rate equation:

${\displaystyle {\frac {\partial N_{it}(t)}{\partial t}}=k_{f}(N_{0}-N_{it}(t))-k_{r}N_{it}(t)\cdot N_{X}(0,t)^{1/a}}$     (3)

Where:

• ${\displaystyle N_{0}}$ – Initial number of Si–H bonds
• ${\displaystyle N_{X}(0,t)}$ – Surface concentration of hydrogen at interface
• ${\displaystyle a}$ – Reaction order (typically 1 or 2)
• ${\displaystyle k_{f}}$ – Forward rate constant
• ${\displaystyle k_{r}}$ – Reverse rate constant

Modern TCAD(Technology Computer-Aided Design) frameworks, implement extended versions of these models, enabling accurate simulation of degradation caused by NBTI.

Circuit-Level Effects

NBTI increases the threshold voltage of pMOS transistors over time, reducing their drive strength. In digital logic circuits, this leads to increased propagation delays and timing degradation. These changes can accumulate across logic paths, impacting setup and hold margins. BTI affects sequential and combinational circuits quite differently and the degradation varies to 5X in between operating conditions. ^[4]

^[5]

Stress and Recovery

NBTI degradation consists of a stress phase and a recovery phase. During stress, Si–H bonds at the interface break under negative gate bias and elevated temperature, generating interface traps. When stress is removed, some of the hydrogen species diffuse back and re-passivate the broken bonds, leading to partial recovery.

The recovery is typically incomplete and strongly dependent on device type, temperature, and stress duration. PMOS transistors tend to show slower and less reversible recovery than NMOS due to differences in hydrogen diffusivity and interface chemistry.^{[6] [3]}

NBTI in Advanced Nodes

As technology scales below 14 nm, NBTI remains a critical reliability concern. FinFETs show increased NBTI degradation due to higher vertical electric fields and localized self-heating, which accelerates trap generation. Studies show degradation up to 25% in 7 nm FinFETs due to NBTI and Hot Carrier Injection (HCI) effects.^[7][8]

Gate-All-Around FETs (GAAFETs) offer improved recovery characteristics compared to FinFETs due to more symmetric hydrogen diffusion and re-passivation. Devices with (100) oriented channels in particular show ~20% lower NBTI degradation under identical stress conditions.^[9]

Security Implications

NBTI has been exploited in hardware security attacks, particularly in cloud-deployed FPGAs. The "pentimento" effect refers to data remanence caused by BTI-induced changes in delay characteristics of LUTs, which can allow adversaries to reconstruct previously programmed values.^[10][11]

Additionally, NBTI can be used to trigger hardware Trojans or fault injection attacks by inducing accelerated degradation on specific logic paths. Attackers can exploit stress patterns or aging-aware layouts to control circuit behavior over time. ^[12][13]

See also

• Hot carrier injection
• Electromigration

References

1. S. Entner, “Time Exponent in Power-Law Modeling of NBTI”, TU Wien, 2010.
2. S. Entner, “Reaction–Diffusion Model”, TU Wien, 2010.
3. S. Mahapatra and N. Parihar, “A review of NBTI mechanisms and models,” *Microelectronics Reliability*, vol. 81, pp. 127–135, 2018. doi:10.1016/j.microrel.2018.02.021
4. J. Fang and S. S. Sapatnekar, “The impact of BTI variations on timing,” *IEEE Transactions on Device and Materials Reliability*, vol. 13, no. 1, pp. 277–286, 2013. doi:10.1109/TDMR.2013.2248124
5. W. Wang et al., “The impact of NBTI on circuit performance,” in *Design Automation Conference (DAC)*, 2007, pp. 364–369. [1]
6. P. Hehenberger et al., “Recovery of NBTI and PBTI stress,” in *IEEE International Integrated Reliability Workshop (IIRW)*, 2010, pp. 8–11. [2]
7. K. Choi et al., “Reliability on evolutionary FinFET CMOS,” in *International Electron Devices Meeting (IEDM)*, 2020. [3]
8. C. Young et al., “FinFETs: Performance and reliability,” *Solid-State Electronics*, vol. 78, pp. 2–10, 2012. doi:10.1016/j.sse.2012.05.003
9. S. Kim et al., “Reliability assessment of 3nm GAA,” in *IEEE International Reliability Physics Symposium (IRPS)*, 2023. [4]
10. C. Drewes et al., “Pentimento: Data remanence in cloud FPGAs,” in *Architectural Support for Programming Languages and Operating Systems (ASPLOS)*, 2024, pp. 862–878. [5]
11. K. M. Zick et al., “LUT burn-in leakage,” in *Field-Programmable Logic and Applications (FPL)*, 2014, pp. 1–6. [6]
12. S. F. Mossa et al., “NBTI-induced Trojan in 3D ICs,” *Integration*, vol. 58, pp. 116–124, 2017. doi:10.1016/j.vlsi.2017.01.002
13. A. Sengupta et al., “NBTI threat analysis on DSP cores,” in *IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)*, 2017, pp. 11–14. [7]

• J.H. Stathis, S. Mahapatra, and T. Grasser, “Controversial issues in negative bias temperature instability”, Microelectronics Reliability, vol 81, pp. 244–251, Feb. 2018. doi:10.1016/j.microrel.2017.12.035
• T. Grasser et al., “The paradigm shift in understanding the bias temperature instability: From reaction–diffusion to switching oxide traps”, IEEE Transactions on Electron Devices 58 (11), pp. 3652–3666, Nov. 2011. doi:10.1109/TED.2011.2164543 Bibcode:2011ITED...58.3652G
• D.K. Schroder, “Negative bias temperature instability: What do we understand?”, Microelectronics Reliability, vol. 47, no. 6, pp. 841–852, June 2007. doi:10.1016/j.microrel.2006.10.006
• Schroder, Dieter K. (August 2005). "Negative Bias Temperature Instability (NBTI): Physics, Materials, Process, and Circuit Issues" (PDF).
• JH Stathis and S Zafar, “The negative bias temperature instability in MOS devices: A review”, Microelectronics Reliability, vol 46, no. 2, pp. 278–286, Feb. 2006. doi:10.1016/j.microrel.2005.08.001
• M. Alam and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation”, Microelectronics Reliability, vol. 45, no. 1, pp. 71–81, Jan. 2005. doi:10.1016/j.microrel.2004.03.019
• S. Entner, “Time Exponent in Power-Law Modeling of NBTI”, TU Wien, 2010.
• S. Entner, “Reaction–Diffusion Model”, TU Wien, 2010.
• S. Mahapatra and N. Parihar, “A review of NBTI mechanisms and models,” *Microelectronics Reliability*, vol. 81, pp. 127–135, 2018. doi:10.1016/j.microrel.2018.02.021 [8]
• R. Tiwari et al., “TCAD framework to estimate the NBTI degradation in FinFET and GAA NS-FET,” in *IEEE International Symposium on Semiconductor Manufacturing (SISPAD)*, 2019, pp. 1–4. [9]
• J. Fang and S. S. Sapatnekar, “The impact of BTI variations on timing,” *IEEE Transactions on Device and Materials Reliability*, vol. 13, no. 1, pp. 277–286, 2013. doi:10.1109/TDMR.2013.2248124 [10]
• W. Wang et al., “The impact of NBTI on circuit performance,” in *Design Automation Conference (DAC)*, 2007, pp. 364–369. [11]
• P. Hehenberger et al., “Recovery of NBTI and PBTI stress,” in *IEEE International Integrated Reliability Workshop (IIRW)*, 2010, pp. 8–11. [12]
• K. Choi et al., “Reliability on evolutionary FinFET CMOS,” in *International Electron Devices Meeting (IEDM)*, 2020. [13]
• C. Young et al., “FinFETs: Performance and reliability,” *Solid-State Electronics*, vol. 78, pp. 2–10, 2012. doi:10.1016/j.sse.2012.05.003 [14]
• S. Kim et al., “Reliability assessment of 3nm GAA,” in *IEEE International Reliability Physics Symposium (IRPS)*, 2023. [15]
• C. Drewes et al., “Pentimento: Data remanence in cloud FPGAs,” in *Architectural Support for Programming Languages and Operating Systems (ASPLOS)*, 2024, pp. 862–878. [16]
• K. M. Zick et al., “LUT burn-in leakage,” in *Field-Programmable Logic and Applications (FPL)*, 2014, pp. 1–6. [17]
• S. F. Mossa et al., “NBTI-induced Trojan in 3D ICs,” *Integration*, vol. 58, pp. 116–124, 2017. doi:10.1016/j.vlsi.2017.01.002 [18]
• A. Sengupta et al., “NBTI threat analysis on DSP cores,” in *IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)*, 2017, pp. 11–14. [19]