MOSIS

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Not to be confused with Moses.

MOSIS (Metal Oxide Semiconductor Implementation Service) is multi-project wafer service that provides metal–oxide–semiconductor (MOS) chip design tools and related services that enable universities, government agencies, research institutes and businesses to prototype chips efficiently and cost-effectively.

Operated by the University of Southern California's Information Sciences Institute (ISI), MOSIS combines customers' orders onto shared multi-project wafers that speed production and reduce costs compared with underutilized single-project wafers. Customers are able to debug and adjust designs, or to commission small-volume runs, without making major production investments. Fabrication costs are also shared by combining multiple designs from a single customer onto one "mask set," or wafer template. According to MOSIS, by the end of 2016, the service has delivered more than 60,000 integrated circuit designs.[1]

Funded by DARPA,[2] MOSIS was created in 1980[3] by ISI's Danny Cohen, an Internet pioneer who also developed Voice over Internet Protocol and Video over Internet Protocol.[4] It was based on the revolutionary VLSI design methodology of Carver Mead and Lynn Conway, who pioneered and/or popularized the use of technology-independent design rules and modular cell-based, hierarchical system design, testing this new approach to rapid prototyping and short-run fabrication at Xerox PARC.[5] One of the first e-commerce providers, MOSIS also launched the "fabless foundry" industry, in which vendors outsource chip fabrication rather than manufacturing them in-house.[6] Thousands of students also have learned chip design in MOSIS-associate programs.[7]

Many early MOSIS users were students trying IC layout techniques from the seminal book Introduction to VLSI Design (ISBN 0-201-04358-0) published in 1980 by Caltech professor Carver Mead[8] and PARC researcher Lynn Conway, who taught the world's first VLSI class at MIT.[9][10] Some early reduced instruction set computing (RISC) processors such as MIPS (1984) and SPARC (1987) were run through MOSIS during their early design and testing phases.

MOSIS in the 1980s

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After the transfer of Xerox PARC's multi-project wafer (MPW) technology to USC/ISI[3], the MOSIS Project was created, and the first trial run conducted in August 1980[11]:

In August 1980 MOSIS accepted designs for the first fabrication run using the software developed for automatic interaction with users. This run had 65 projects submitted by designers from 8 organizations: ISI, UCLA, Caltech, Jet Propulsion Lab, Stanford University, National Bureau of Standards, Carnegie-Mellon University and Washington University at St. Louis. These projects were packed into 18 dies on the wafer.

The service became operational in January 1981, with 5-micron nMOS as the first fabrication technology offered; designs were submitted in Caltech Intermediate Form via the ARPANET.[11] By 1983, more than forty organizations were using the service.[12] Chips were returned to designers approximately a month after the close of a fabrication run.

Over the course of the 1980s, more than 12,000 projects were fabricated through the MOSIS service.[13] After the initial 5-micron, 1-metal layer nMOS service, new technologies were introduced, advancing to 1.2-micron, 2-metal layer CMOS by 1988. At the end of the 1980s, gallium arsenide (GaAs) fabrication service was added.[14]

MOSIS Projects in 1980s [13]
Technology
Size (μm) Layers Type 1981 1982 1983 1984 1985 1986 1987 1988 1989 TOTALS
NMOS 5 1M D 238 441 679
NMOS 4 1M D 20 283 1199 1035 234 18 2789
NMOS 3 1M D 63 56 162 439 309 131 20 1180
CMOS 5 1M D 22 45 67
CMOS 3 2M D 949 1113 887 710 231 3890
CMOS 3 1M A 22 437 106 146 83 5 799
CMOS-SOS 4 D 62 11 73
CMOS 2 2M D 71 225 396 615 1307
CMOS 2 2M A 185 934 1119
CMOS 1.6 2M D 15 70 86 55 226
CMOS 1.2 2M D 27 45 72
TOTALS 258 809 1332 1634 1790 1683 1396 1429 1880
GRAND TOTAL 12,201

See also

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References

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  1. ^ "What is MOSIS?". Retrieved 2025-09-16.
  2. ^ "The MOSIS Service of ISI and SkyWater Collaborate on Silicon IC Design Enablement and Manufacturing Service". USC Viterbi | School of Engineering. Retrieved 2024-05-30.
  3. ^ a b Conway, Lynn (2012). "Reminiscences of the VLSI Revolution: How a Series of Failures Triggered a Paradigm Shift in Digital Design". IEEE Solid-State Circuits Magazine. 4 (4). IEEE: 8–31. doi:10.1109/MSSC.2012.2215752. Retrieved 2025-09-12.
  4. ^ "Danny Cohen Engineered the Internet to Take Flight". Wired.
  5. ^ "Lynn's Story". Retrieved 2018-03-10.
  6. ^ "Information Sciences Institute - Timeline". Archived from the original on 2013-11-26.
  7. ^ "USC Viterbi School of Engineering : MOSIS Turns 25". Archived from the original on 2006-09-01.
  8. ^ "Winners' Circle: Carver Mead". Archived from the original on 2014-03-05. Retrieved 2005-04-28.
  9. ^ "M.I.T. VLSI Systems Design Class". Retrieved 2018-03-10.
  10. ^ "IEEE History Center - Lynn Conway". 2003-01-02. Archived from the original on 2006-06-18. Retrieved 2004-05-18.
  11. ^ a b Uncapher, Keith W. (August 1981). 1980 Annual Technical Report: A Research Program in Computer Technology, Volume 2 (Technical report). USC/ISI. ISI/SR-81-20. Retrieved 2025-09-16.
  12. ^ Uncapher, Keith W. (July 1984). 1983 Annual Technical Report: A Research Program in Computer Technology, Volume 2 (Technical report). USC/ISI. ISI/SR-84-138. Retrieved 2025-09-16.
  13. ^ a b Van Atta, Richard H; Reed, Sidney G.; Deitchman, Seymour J. (March 1991). DARPA Technical Accomplishments. Volume 2. An Historical Review of Selected DARPA Projects (Technical report). INSTITUTE FOR DEFENSE ANALYSES ALEXANDRIA VA. Retrieved 2025-09-16.
  14. ^ Long, Stephen I.; Butner, Steven E. (May 1990). GaAs IC fabrication with MOSIS-a user's perspective. IEEE International Symposium on Circuits and Systems. New Orleans: IEEE. doi:10.1109/ISCAS.1990.112532. Retrieved 2025-09-17.
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