Ferroelectric flash memory
Ferroelectric flash memory, (ferroelectric NAND, FeNAND, or FeFET-based NAND), is an emerging non-volatile memory technology that incorporates ferroelectric materials (typically doped hafnium oxide, HfO
2) into NAND flash-like architectures. It addresses limitations of conventional charge-trap NAND flash, such as high power consumption, limited endurance, and scaling, by leveraging ferroelectric polarization for data storage. Unlike traditional ferroelectric RAM (FeRAM), which uses a one transistor, one capacitor (1T-1C) structure for random-access memory, ferroelectric flash employs ferroelectric field-effect transistors (FeFETs) in string architectures similar to 3D NAND. This enables higher density, lower operating voltages, and potential for multi-level cell (MLC) or triple-level cell (TLC) operation.[1]
Some 20 different architectures were under development as of 2025.[2]
History
[edit]Research on ferroelectric transistors began in the 1950s–1960s. Practical development stalled due to material incompatibility with CMOS processes.[3] Early HfO
2 prototypes featured a narrow memory window (the write voltage was only slightly higher than the read voltage). This defeated efforts to read and write multiple bits to a single silicon cell.[2]
The discovery of ferroelectricity in doped HfO
2 thin films in 2011 revived interest, as HfO
2 is CMOS-compatible and scalable below 10 nm. Early proposals for FeNAND appeared in the 2000s–2010s, with prototypes using perovskite materials such as PZT or SBT. The shift to HfO
2 enabled 3D integration. Key milestones include:[4]
- In 2012, HfO
2 FeFETs were demonstrated at 28 nm - In 2021, the first CMOS-compatible FeNAND arrays were reported[5]
- From 2023–2025, prototypes achieved low-voltage operation, high endurance (>10¹² cycles), and multi-bit storage.
- In 2023, SK Hynix added an insulating layer that trapped charges on top of the HfO
2 during write, creating a hybrid conventional and ferroelectric device that widened the memory window to an acceptable 10.5 volts.[2]
Device physics and operation
[edit]Ferroelectrics have a stable, polar electrical orientation that an external electric field can switch. Ferroelectric polarity determines whether an applied voltage can drive electron flow through the adjacent channel. Because ferroelectrics can read and write data at lower voltages, the insulating layers that confine cells can be thinner, enabling as many as 1000 cell layers.[2]
Ferroelectric flash relies on FeFETs, where the gate dielectric includes a ferroelectric layer (e.g., HfZrO or HZO). Data storage occurs via reversible polarization states:
- Polarization shifts the transistor threshold voltage (V_th), creating distinct "on" and "off" states
- Reads are non-destructive (current sensing)
- Writes use low voltages (3–6 V vs. 15–20 V in charge-trap NAND), reducing power consumption
In 3D FeNAND, cells stack vertically like conventional NAND, but ferroelectric gates replace charge-trap layers.
To store or retrieve information from a cell (up to 5 bits), FeNAND uses a vertical "pass voltage" that connects the cells in a column so that it acts like a single wire. To reduce power demand, Samsung replaced the silicon in current-carrying channels with indium-gallium-zinc-oxide, a semiconductor that allows a 96% lower pass current to switch it.[1]
Advantages
[edit]- Lower power: Reduced program/erase voltages and no high pass disturbance
- Higher endurance: 10⁹–10¹² cycles vs. 10³–10⁵ for NAND
- Faster speeds: Sub-10 ns switching in prototypes
- Scalability: Potential for >512 layers and TLC/QLC operation
- Multi-bit capability: Large memory windows (up to 12–17 V in 2025 demos)
Challenges
[edit]- Retention and fatigue: polarization degradation over cycles; mitigated by gate-stack engineering (e.g., Al
₂O
₃ interlayers): - Disturbance in strings: Program/erase interference; solved via band engineering or superlattice structures
- Manufacturing: Precise control of HfO
2 orthorhombic phase; integration with oxide channels (e.g., IGZO) for reliability.
Comparison
[edit]| Aspect | Ferroelectric Flash (FeNAND/FeFET NAND) | FeRAM |
|---|---|---|
| Structure | FeFET strings (3D vertical NAND-like) | 1T-1C capacitor arrays |
| Density | High (potential Tb/mm²) | Low (Mb range, planar limits) |
| Read | Non-destructive | Destructive (write-after-read) |
| Endurance | 10⁹–10¹² cycles | >10¹⁵ cycles |
| Speed | ns-scale program/erase | ns-scale, but array-limited |
| Power | Very low (no high pass voltage) | Low |
| Status | Research/prototype | Commercial (niche) |
Applications
[edit]The technology has potential in AI edge devices, hyperscale storage, and low-latency NVM. Challenges include reliability, scaling, and cost. Ongoing work (IEDM 2024–2025) focuses on hybrid FeNAND and in-memory computing.
See also
[edit]References
[edit]- ^ a b Yoo, Sijung; Kim, Taek Jung; Nam, Seung-Geol; Kim, Donghoon; Kim, Kihong; Lee, Yunseong; Jung, Moonil; Lee, Kwang-Hee; Choi, Seokhoon; Hyun, Seung Dam; Lee, Min-Hyun; Hong, Seogwoo; Kim, Haesung; Bae, Ki Deok; Lee, Hyangsook (December 2025). "Ferroelectric transistors for low-power NAND flash memory". Nature. 648 (8093): 320–326. doi:10.1038/s41586-025-09793-3. ISSN 1476-4687.
- ^ a b c d Service, Robert F. (December 17, 2025). "New materials could supercharge computer memory chips". www.science.org. Retrieved 2025-12-20.
- ^ Kim, Min-Kyu; Kim, Ik-Jyae; Lee, Jang-Sik (2021-01-13). "CMOS-compatible ferroelectric NAND flash memory for high-density, low-power, and high-speed three-dimensional memory". Science Advances. 7 (3): eabe1341. doi:10.1126/sciadv.abe1341. PMC 7806215. PMID 33523886.
{{cite journal}}: CS1 maint: article number as page number (link) - ^ Kim, Giuk; Lee, Sangho; Choi, Hyojun; Jung, Yangjin; Kim, Woongjin; Park, Sanghyun; Seo, Kwangyou; Kim, Kwangsoo; Kim, Wanki; Ha, Daewon; Shin, Mincheol; Ahn, Jinho; Jeon, Sanghun (2025). "Middle Interlayer Engineered Ferroelectric NAND Flash Overcoming Reliability and Stability Bottlenecks for Next-Generation High-Density Storage Systems". Advanced Science. 12 (40): e10155. doi:10.1002/advs.202510155. ISSN 2198-3844. PMC 12561253. PMID 40847772.
{{cite journal}}: CS1 maint: article number as page number (link) - ^ Park, Hyeon Woo; Lee, Jae-Gil; Hwang, Cheol Seong (2021). "Review of ferroelectric field-effect transistors for three-dimensional storage applications". Nano Select. 2 (6): 1187–1207. doi:10.1002/nano.202000281. ISSN 2688-4011.
External links
[edit]- Yoon, Sunghyun (August 8, 2023). "QLC Programmable 3D Ferroelectric NAND Flash Memory by Memory Window Expansion using Cell Stack Engineering". SK Hynix.